1. Field of the Invention
The present invention relates to a manufacturing method for an integrated circuit including different types of gate stacks, a corresponding intermediate integrated circuit structure and a corresponding integrated circuit.
2. Description of the Related Art
Non-volatile semiconductor memories are nowadays used in a broad variety of electronic devices such as cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and many other electronic devices.
Electrically erasable programmable read-only memories (EEPROMs) and flash memories are the mainly used non-volatile semiconductor memories.
EEPROMs and flash memories utilize a charge storage region, namely floating gate region or charge trapping region, that is positioned above and insulated from a channel region in a semiconductor substrate. A control gate is provided over and insulated from the floating gate. The floating gate can store charges and can therefore be programmed/erased between two states, i.e., binary “1” and binary “0”. Recently, also multi-level non-volatile memory cells have been developed.
As charge storage stacks in non-volatile memories, nowadays SONOS (silicon-oxide-nitride-oxide-silicon) and TANOS (tantal nitride-aluminum oxide-nitride-oxide-silicon) stacks are frequently used. In these stacks, the silicon nitride layer serves as charge storage layer.
In so-called NAND flash memories, NAND strings of non-volatile memory cells are connected in series. One end of such NAND strings is connected to a common bitline and a common source line by respective select transistors having select gates which are different from the charge storage gate stacks of the memory cells.
With increasing integration smaller than 60 nm it becomes more and more a challenging task to have a robust process flow wherein the manufacture of the charge storage stacks, the select gate stacks and the peripheral transistor gate stacks can be easily integrated in the manufacturing steps of the memory.
In the Figures, identical reference signs denote equivalent or functionally equivalent components.